Tue Jul 18 U-boot side is fixed, marvell switch device can be accessed via mii tool without touching uboot source. Marvell 88E is a switch-chip 10 port fastethernet that is connected by an mdi to my sam9x The hardware of the board is defined by a device tree that was originaly created by the yocto project open embedded. Hash tables configured established bind TCP: This file is automatically generated by Xilinx.
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Registered protocol family 2 TCP established hash dssa entries: There is a driver called dsa in the linux kernel making the ports of the switch available in linux for management. However, it is not tried yet.
Device Tree entry for Marvell DSA – Welcome to AT91SAM Community Discussions
This is next information about thread progress, only reply to me from myself again!! Still kernel side, same rsa exits; but in different way The driver requires me to define a mii-handle.
Total of 2 processors activated After that, dea is required to up eth1, e. Because the connection between zynq and port5 of the switch is rgmii-id, there should be delay between data and clock signals.
Build-time adjustment of leaf fanout to Is there anyone can provide some suggestion or solution about ds issue related to integration marvell switch, pls?? A switch example by Atmel would be great, but I do not know if they ever put a switch on one of there eval boards?
How to make Marvell switch mv88e6352 work with kernel 4.1.15 on IMX6Q ?
Registered protocol family 10 update-rc. Cadence GEM rev 0x at 0xeb irq Freeing unused kernel memory: Testing write buffer coherency: Port0-toPort4 are normal PHY interface for outside phy interface.
Copyright c – Intel Corporation. Before this was done manually using mii command at u-boot stage mii write 0x15 0x01 0xCbecause the kernel could not set fixed-link port5 register for enable TX and RX clk delay. After some hard efforts, found the problems on both u-boot and kernel sides.
Solved: zynq and marvell dsa 88e integration, device t – Community Forums
We have been trying to up ethernet solution for those zynq boards. The original petalinux device tree config which is generated after petalinux-build is included. Hi, I switched to Vivado You can find it attached. Margell protocol family 10 IPv6: Below, I put the gem0 related part of the zynq Since switch port5 fixed link speed is mbps, but gmii2rgmii speed is 10mbps, GEM1 mrvell not ping with PC.
CLS 0 bytes, default 64 hw perfevents: Below you can find the steps for the MIO connected switch integratio n. So we use as workaround but we are not happy with this.
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. Now, as you can see below, we can see the 88e registers and access them. Those are the ethernet interfaces to the outside.
Buti still kernel side is problem, i have tried lots of alternative device-tree configs, but the petalinux gives same error always.
Please upgrade to a Xilinx. For example the freescale driver is able to do so: Registered udp transport module.